PIC18F2480_09 Datasheet, PDF (162/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
14.2 Timer2 Interrupt
Timer2 also can generate an optional device interrupt.
The Timer2 output signal (TMR2 to PR2 match)
provides the input for the 4-bit output counter/post-
scaler. This counter generates the TMR2 match inter-
rupt flag which is latched in TMR2IF (PIR1<1>). The
interrupt is enabled by setting the TMR2 Match Inter-
rupt Enable bit, TMR2IE (PIE1<1>).
A range of 16 postscale options (from 1:1 through 1:16
inclusive) can be selected with the postscaler control
bits, T2OUTPS<3:0> (T2CON<6:3>).
FIGURE 14-1:
TIMER2 BLOCK DIAGRAM
T2OUTPS<3:0>
2
T2CKPS<1:0>
FOSC/4
1:1, 1:4, 1:16
Prescaler
Internal Data Bus
4
Reset
TMR2
8
14.3 TMR2 Output
The unscaled output of TMR2 is available primarily to
the CCP modules, where it is used as a time base for
operations in PWM mode.
Timer2 can be optionally used as the shift clock source
for the MSSP module operating in SPI mode. Addi-
tional information is provided in Section 18.0 “Master
Synchronous Serial Port (MSSP) Module”.
1:1 to 1:16
Postscaler
TMR2/PR2
Match
Comparator
8
Set TMR2IF
TMR2 Output
(to PWM or MSSP)
PR2
8
TABLE 14-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Name Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE TMR0IF INT0IF RBIF
55
PIR1
PSPIF⁽¹⁾
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
58
PIE1
PSPIE⁽¹⁾
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
58
IPR1
PSPIP⁽¹⁾
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP
58
TMR2 Timer2 Register
56
T2CON
— T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 56
PR2 Timer2 Period Register
56
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
Note 1: These bits are unimplemented on PIC18F2X80 devices; always maintain these bits clear.
DS39637D-page 162
© 2009 Microchip Technology Inc.