PIC18F2480_09 Datasheet, PDF (60/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
TABLE 5-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register
Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
RXB1SIDH 2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
RXB1CON 2480 2580 4480 4580 000- 0000
000- 0000
uuu- uuuu
TXB0D7
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D6
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D5
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D4
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D3
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D2
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D1
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0D0
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0DLC
2480 2580 4480 4580 -x-- xxxx
-u-- uuuu
-u-- uuuu
TXB0EIDL
2480 2580 4480 4580
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0EIDH 2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
-uuu uuuu
TXB0SIDL
2480 2580 4480 4580
xxx- x-xx
uuu- u-uu
uuu- u-uu
TXB0SIDH 2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB0CON
2480 2580 4480 4580
0000 0-00
0000 0-00
uuuu u-uu
TXB1D7
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D6
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D5
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D4
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D3
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D2
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D1
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1D0
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1DLC
2480 2580 4480 4580 -x-- xxxx
-u-- uuuu
-u-- uuuu
TXB1EIDL
2480 2580 4480 4580
xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1EIDH 2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
uuuu uuuu
TXB1SIDL
2480 2580 4480 4580
xxx- x-xx
uuu- u-uu
uuu- uu-u
TXB1SIDH 2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
-uuu uuuu
TXB1CON
2480 2580 4480 4580
0000 0-00
0000 0-00
uuuu u-uu
TXB2D7
2480 2580 4480 4580 xxxx xxxx
uuuu uuuu
0uuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 5-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.
DS39637D-page 60
© 2009 Microchip Technology Inc.