PIC18F2480_09 Datasheet, PDF (172/490 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PIC18F2480/2580/4480/4580
TABLE 16-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF
RBIF
55
RCON
IPEN SBOREN⁽³⁾
—
RI
TO
PD
POR
BOR
56
IPR1
PSPIP
ADIP
RCIP
TXIP
SSPIP CCP1IP TMR2IP TMR1IP
58
PIR1
PSPIF
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF
58
PIE1
IPR2
PIR2
PIE2
PSPIE
OSCFIP
OSCFIF
OSCFIE
ADIE
CMIP⁽²⁾
CMIF⁽²⁾
CMIE⁽²⁾
RCIE
—
—
—
TXIE
EEIP
EEIF
EEIE
SSPIE CCP1IE TMR2IE TMR1IE
58
BCLIP HLVDIP TMR3IP ECCP1IP⁽²⁾ 58
BCLIF HLVDIF TMR3IF ECCP1IF⁽²⁾ 58
BCLIE HLVDIE TMR3IE ECCP1IE⁽²⁾ 57
TRISB
PORTB Data Direction Register
58
TRISC
PORTC Data Direction Register
58
TMR1L
Timer1 Register Low Byte
56
TMR1H
Timer1 Register High Byte
56
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
56
TMR3H
Timer3 Register High Byte
57
TMR3L
T3CON
Timer3 Register Low Byte
57
RD16 T3ECCP1⁽¹⁾ T3CKPS1 T3CKPS0 T3CCP1⁽¹⁾ T3SYNC TMR3CS TMR3ON
57
CCPR1L
Capture/Compare/PWM Register 1 Low Byte
57
CCPR1H
Capture/Compare/PWM Register 1 High Byte
57
CCP1CON
—
—
DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
57
ECCPR1L⁽¹⁾ Enhanced Capture/Compare/PWM Register 1 Low Byte
57
ECCPR1H⁽¹⁾ Enhanced Capture/Compare/PWM Register 1 High Byte
57
ECCP1CON⁽¹⁾ EPWM1M1 EPWM1M0 EDC1B1 EDC1B0 ECCP1M3 ECCP1M2 ECCP1M1 ECCP1M0
57
Legend:
Note 1:
2:
3:
— = unimplemented, read as ‘0’. Shaded cells are not used by capture, compare, Timer1 or Timer3.
These bits or registers are available on PIC18F4X80 devices only.
These bits are available on PIC18F4X80 devices and reserved on PIC18F2X80 devices.
The SBOREN bit is only available when CONFIG2L<1:0> = 01; otherwise, it is disabled and reads as ‘0’. See
Section 5.4 “Brown-out Reset (BOR)”.
DS39637D-page 172
© 2009 Microchip Technology Inc.