PIC16F946 Datasheet, PDF (87/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

5.4 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer. For simplicity, this counter will be referred to as
“prescaler” throughout this data sheet. The prescaler
assignment is controlled in software by the control bit
PSA (OPTION_REG<3>). Clearing the PSA bit will
assign the prescaler to Timer0. Prescale values are
selectable via the PS<2:0> bits (OPTION_REG<2:0>).
The prescaler is not readable or writable. When
assigned to the Timer0 module, all instructions writing
to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF 1, x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer.
5.4.1
SWITCHING PRESCALER
ASSIGNMENT
The prescaler assignment is fully under software control
(i.e., it can be changed “on-the-fly” during program
execution). To avoid an unintended device Reset, the
following instruction sequence (Example 5-1 and
Example 5-2) must be executed when changing the
prescaler assignment from Timer0 to WDT.
PIC16F946
EXAMPLE 5-1:
CHANGING PRESCALER
(TIMER0 → WDT)
BCF
STATUS,RP0
CLRWDT
CLRF TMR0
BSF
STATUS,RP0
;Bank 0
;Clear WDT
;Clear TMR0 and
; prescaler
;Bank 1
MOVLW b’00101111’
MOVWF OPTION_REG
CLRWDT
MOVLW
MOVWF
BCF
b’00101xxx’
OPTION_REG
STATUS,RP0
;Required if desired
; PS2:PS0 is
; 000 or 001
;
;Set postscaler to
; desired WDT rate
;Bank 0
To change prescaler from the WDT to the TMR0
module, use the sequence shown in Example 5-2. This
precaution must be taken even if the WDT is disabled.
EXAMPLE 5-2:
CHANGING PRESCALER
(WDT → TIMER0)
CLRWDT
BSF
STATUS,RP0
;Clear WDT and
; prescaler
;Bank 1
MOVLW b’xxxx0xxx’
MOVWF OPTION_REG
BCF
STATUS,RP0
;Select TMR0,
; prescale, and
; clock source
;
;Bank 0
TABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
01h
TMR0
Timer0 Module register
xxxx xxxx uuuu uuuu
0Bh/10Bh INTCON
GIE
PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
81h
OPTION_REG RBPU INTEDG T0CS T0SE PSA
PS2
PS1
PS0 1111 1111 1111 1111
85h
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the Timer0 module.
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 85