PIC16F946 Datasheet, PDF (18/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
TABLE 2-4: PIC16F946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOR
Reset
Value on
all other
Resets⁽¹⁾
Bank 3
180h
INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx xxxx xxxx
181h
OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 1111 1111
182h
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
183h
STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
184h
FSR
Indirect Data Memory Address Pointer
xxxx xxxx uuuu uuuu
185h
TRISF
TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 1111 1111 1111 1111
186h
TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
187h
TRISG
—
—
TRISG5 TRISG4 TRISG3 TRISG2 TRISG1 TRISG0 --11 1111 --11 1111
188h
PORTF
RF7
RF6
RF5
RF4
RF3
RF2
RF1
RF0 xxxx xxxx uuuu uuuu
189h
PORTG
—
—
RG5
RG4
RG3
RG2
RG1
RG0 --xx xxxx --uu uuuu
18Ah PCLATH
—
—
— Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
18Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000x
18Ch EECON1
EEPGD
—
—
—
WRERR WREN
WR
RD 0--- x000 0--- q000
18Dh EECON2
EEPROM Control Register 2 (not a physical register)
---- ---- ---- ----
190h
LCDDATA12
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu
COM0 COM0 COM0 COM0 COM0 COM0 COM0 COM0
191h
LCDDATA13
SEG39 SEG38 SEG37 SEG36 SEG35 SEG34
COM0 COM0 COM0 COM0 COM0 COM0
SE33
COM0
SEG32 xxxx xxxx uuuu uuuu
COM0
192h
LCDDATA14
—
—
—
—
—
—
SEG41 SEG40 ---- --xx ---- --uu
COM0 COM0
193h
LCDDATA15
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
194h
LCDDATA16
SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu
COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1
195h
LCDDATA17
—
—
—
—
—
—
SEG41 SEG40 ---- --xx ---- --uu
COM1 COM1
196h
LCDDATA18
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
197h
LCDDATA19
SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu
COM2 COM2 COM2 COM2 COM2 COM2 COM2 COM2
198h
LCDDATA20
—
—
—
—
—
—
SEG41 SEG40 ---- --xx ---- --uu
COM2 COM2
199h
LCDDATA21
SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 xxxx xxxx uuuu uuuu
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
19Ah
LCDDATA22
SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 xxxx xxxx uuuu uuuu
COM3 COM3 COM3 COM3 COM3 COM3 COM3 COM3
19Bh
19Ch
19Dh
19Eh
LCDDATA23
LCDSE3⁽²⁾
LCDSE4⁽²⁾
LCDSE5⁽²⁾
—
SE31
SE39
—
—
SE30
SE38
—
—
SE29
SE37
—
—
SE28
SE36
—
—
SE27
SE35
—
—
SE26
SE34
—
SEG41
COM3
SE25
SE33
SE41
SEG40
COM3
SE24
SE32
SE40
---- --xx ---- --uu
0000 0000 uuuu uuuu
0000 0000 uuuu uuuu
---- --00 ---- --uu
19Fh
—
Unimplemented
—
—
Legend:
Note 1:
2:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
This register is only initialized by a POR or BOR reset and is unchanged by other Resets.
DS41265A-page 16
Preliminary
© 2005 Microchip Technology Inc.