PIC16F946 Datasheet, PDF (198/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
16.3.4 TIME-OUT SEQUENCE
On power-up, the time-out sequence is as follows: first,
PWRT time-out is invoked after POR has expired, then
OST is activated after the PWRT time-out has expired.
The total time-out will vary based on oscillator configu-
ration and PWRTE bit status. For example, in EC mode
with PWRTE bit erased (PWRT disabled), there will be
no time-out at all. Figure 16-4, Figure 16-5 and Figure
16-6 depict time-out sequences. The device can exe-
cute code from the INTOSC while OST is active, by
enabling Two-Speed Start-up or Fail-Safe Monitor (see
Section 4.6.2 “Two-Speed Start-up Sequence” and
Section 4.7 “Fail-Safe Clock Monitor”).
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, the time-outs will expire. Then,
bringing MCLR high will begin execution immediately
(see Figure 16-5). This is useful for testing purposes or
to synchronize more than one PIC16F946 device
operating in parallel.
Table 16-5 shows the Reset conditions for some
special registers, while Table 16-5 shows the Reset
conditions for all the registers.
16.3.5 POWER CONTROL (PCON)
REGISTER
The Power Control (PCON) register (address 8Eh) has
two Status bits to indicate what type of Reset that last
occurred.
Bit 0 is BOR (Brown-out Reset). BOR is unknown on
Power-on Reset. It must then be set by the user and
checked on subsequent Resets to see if BOR = 0,
indicating that a Brown-out has occurred. The BOR
Status bit is a “don’t care” and is not necessarily
predictable if the brown-out circuit is disabled
(BOREN<1:0> = 00 in the Configuration Word register).
Bit 1 is POR (Power-on Reset). It is a ‘0’ on Power-on
Reset and unaffected otherwise. The user must write a
‘1’ to this bit following a Power-on Reset. On a
subsequent Reset, if POR is ‘0’, it will indicate that a
Power-on Reset has occurred (i.e., VDD may have
gone too low).
For more information, see Section 16.3.3 “Brown-Out
Reset (BOR)”.
TABLE 16-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator Configuration
Power-up
PWRTE = 0 PWRTE = 1
XT, HS, LP⁽¹⁾
TPWRT + 1024 •
TOSC
RC, EC, INTOSC
TPWRT
Note 1: LP mode with T1OSC disabled.
1024 • TOSC
—
Brown-out Reset
PWRTE = 0
TPWRT + 1024 •
TOSC
TPWRT
PWRTE = 1
1024 • TOSC
—
Wake-up from
Sleep
1024 • TOSC
—
TABLE 16-2: PCON BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
Condition
0
u
1
1 Power-on Reset
1
0
1
1 Brown-out Reset
u
u
0
u WDT Reset
u
u
0
0 WDT Wake-up
u
u
u
u MCLR Reset during normal operation
u
u
1
0 MCLR Reset during Sleep
Legend: u = unchanged, x = unknown
TABLE 16-3: SUMMARY OF REGISTERS ASSOCIATED WITH BROWN-OUT
Address Name Bit 7 Bit 6 Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets⁽¹⁾
03h
8Eh
Legend:
Note 1:
STATUS IRP RP1 RPO
TO
PD
Z
DC
C 0001 1xxx 000q quuu
PCON
—
—
— SBOREN —
—
POR BOR --01 --qq --0u --uu
u = unchanged, x = unknown, – = unimplemented bit, reads as ‘0’, q = value depends on condition. Shaded cells are
not used by BOR.
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
DS41265A-page 196
Preliminary
© 2005 Microchip Technology Inc.