PIC16F946 Datasheet, PDF (16/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
TABLE 2-2: PIC16F946 SPECIAL FUNCTION REGISTERS SUMMARY BANK 1
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOR
Reset
Value on
all other
Resets⁽¹⁾
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx xxxx xxxx
81h OPTION_REG RBPU INTEDG T0CS
T0SE
PSA
PS2
PS1
PS0 1111 1111 1111 1111
82h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 0000 0000
83h STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
84h FSR
Indirect Data Memory Address Pointer
xxxx xxxx uuuu uuuu
85h TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
86h TRISB
TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
88h TRISD
89h TRISE
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2
TRISE7 TRISE6 TRISE5 TRISE4 TRISE3⁽³⁾ TRISE2
TRISD1
TRISE1
TRISD0
TRISE0
1111 1111 1111 1111
1111 1111 1111 1111
8Ah PCLATH
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
8Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000x
8Ch PIE1
EEIE
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2
OSFIE C2IE
C1IE
LCDIE
—
LVDIE
—
CCP2IE 0000 -0-0 0000 -0-0
8Eh PCON
8Fh OSCCON
—
—
—
SBOREN
—
—
POR
BOR ---1 --qq ---u --uu
—
IRCF2 IRCF1 IRCF0 OSTS⁽²⁾
HTS
LTS
SCS -110 q000 -110 x000
90h OSCTUNE
—
—
—
TUN4
TUN3
TUN2
TUN1
TUN0 ---0 0000 ---u uuuu
91h ANSEL
ANS7 ANS6 ANS5 ANS4
ANS3
ANS2
ANS1
ANS0 1111 1111 1111 1111
92h PR2
93h SSPADD
Timer2 Period Register
Synchronous Serial Port (I²C mode) Address Register
1111 1111 1111 1111
0000 0000 0000 0000
94h SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 0000 0000
95h WPUB
WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 1111 1111 1111 1111
96h IOCB
IOCB7 IOCB6 IOCB5 IOCB4
—
—
—
—
0000 ---- 0000 ----
97h CMCON1
—
—
—
—
—
—
T1GSS C2SYNC ---- --10 ---- --10
98h TXSTA
CSRC
TX9
TXEN SYNC
—
BRGH
TRMT
TX9D 0000 -010 0000 -010
99h SPBRG
SPBRG7 SPBRG6 SPBRG5 SPBRG4 SPBRG3 SPBRG2 SPBRG1 SPBRG0 0000 0000 0000 0000
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch CMCON0
C2OUT C1OUT C2INV C1INV
CIS
CM2
CM1
CM0 0000 0000 0000 0000
9Dh VRCON
VREN
—
VRR
—
VR3
VR2
VR1
VR0 0-0- 0000 0-0- 0000
9Eh ADRESL
A/D Result Register Low Byte
xxxx xxxx uuuu uuuu
9Fh ADCON1
—
ADCS2 ADCS1 ADCS0
—
—
—
—
-000 ---- -000 ---
Legend:
Note 1:
2:
3:
– = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
The value of the OSTS bit is dependent on the value of the Configuration Word (CONFIG) of the device. See Section 4.0 “Clock
Sources”.
Bit is read-only; TRISE = 1 always.
DS41265A-page 14
Preliminary
© 2005 Microchip Technology Inc.