PIC16F946 Datasheet, PDF (194/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
16.1 Configuration Bits
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’) to select various
device configurations as shown in Register 16-1.
These bits are mapped in program memory location
2007h.
Note:
Address 2007h is beyond the user
program memory space. It belongs to the
special configuration memory space
(2000h-3FFFh), which can be accessed
only during programming. See
“PIC16F91X/946 Memory Programming
Specification” (DS41244) for more
information.
REGISTER 16-1: CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)
—
bit 13
DEBUG FCMEN IESO BOREN1 BOREN0 CPD
CP MCLRE PWRTE WDTE FOSC2 FOSC1 FOSC0
bit 0
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Unimplemented: Read as ‘1’
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6/ICSPCLK/ICDCK/SEG14 and RB7/ICSPDAT/ICDDAT/SEG13 are dedicated to the debugger
FCMEN: Fail-Safe Clock Monitor Enabled bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled
0 = Internal External Switchover mode is disabled
BOREN<1:0>: Brown-out Reset Selection bits⁽¹⁾
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit (PCON<4>)
00 = BOR disabled
CPD: Data Code Protection bit⁽²⁾
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit⁽³⁾
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: RB3/MCLR/VPP pin function select bit⁽⁴⁾
1 = RB3/MCLR/VPP pin function is MCLR
0 = RB3/MCLR/VPP pin function is digital input, MCLR internally tied to VDD
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled and can be enabled by SWDTEN bit (WDTCON<0>)
FOSC<2:0>: Oscillator Selection bits
111 = RC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI
110 = RCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, RC on RA7/OSC1/CLKI/T1OSI
101 = INTOSC oscillator: CLKO function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI
100 = INTOSCIO oscillator: I/O function on RA6/OSC2/CLKO/T1OSO pin, I/O function on RA7/OSC1/CLKI/T1OSI
011 = EC: I/O function on RA6/OSC2/CLKO/T1OSO pin, CLKI on RA7/OSC1/CLKI/T1OSI
010 = HS oscillator: High-speed crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI
001 = XT oscillator: Crystal/resonator on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI
000 = LP oscillator: Low-power crystal on RA6/OSC2/CLKO/T1OSO and RA7/OSC1/CLKI/T1OSI
Note 1:
2:
3:
4:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire data EEPROM will be erased when the code protection is turned off.
The entire program memory will be erased when the code protection is turned off.
When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled.
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS41265A-page 192
Preliminary
© 2005 Microchip Technology Inc.