PIC16F946 Datasheet, PDF (22/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
2.2.2.4 PIE1 Register
The PIE1 register contains the interrupt enable bits, as
shown in Register 2-1.
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1 – PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS: 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
R/W-0 R/W-0 R/W-0
EEIE
ADIE
RCIE
TXIE
SSPIE CCP1IE TMR2IE TMR1IE
bit 7
bit 0
bit 7
EEIE: EE Write Complete Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 5
RCIE: USART Receive Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 4
TXIE: USART Transmit Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 3
SSPIE: Synchronous Serial Port (SSP) Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enabled
0 = Disabled
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enabled
0 = Disabled
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
DS41265A-page 20
Preliminary
© 2005 Microchip Technology Inc.