PIC16F946 Datasheet, PDF (176/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
14.8 Sleep Operation
In Master mode, all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes from Sleep. After the device returns to
normal mode, the module will continue to trans-
mit/receive data.
In Slave mode, the SPI Transmit/Receive Shift register
operates asynchronously to the device. This allows the
device to be placed in Sleep mode and data to be
shifted into the SPI Transmit/Receive Shift register.
When all 8 bits have been received, the SSP interrupt
flag bit will be set and if enabled, will wake the device
from Sleep.
14.9 Effects of a Reset
A Reset disables the SSP module and terminates the
current transfer.
14.10 Bus Mode Compatibility
Table 14-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 14-1: SPI™ BUS MODES
Standard SPI™
Mode Terminology
Control Bits State
CKP
CKE
0, 0
0, 1
1, 0
1, 1
0
1
0
0
1
1
1
0
There is also a SMP bit which controls when the data is
sampled.
TABLE 14-2: REGISTERS ASSOCIATED WITH SPI™ OPERATION
Address Name
Bit 7
Bit 6 Bit 5
Bit 4
Bit 3 Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on
all other
Resets
0Bh,8Bh. INTCON
GIE
PEIE T0IE
INTE RBIE T0IF
INTF
RBIF 0000 000x 0000 000x
10Bh,18Bh
0Ch
PIR1
EEIF
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
13h
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h
SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
87h
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 1111 1111
8Ch
PIE1
EEIE
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
85h
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 1111 1111 1111 1111
94h
SSPSTAT SMP
CKE
D/A
P
S
R/W
UA
BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
DS41265A-page 174
Preliminary
© 2005 Microchip Technology Inc.