PIC16F946 Datasheet, PDF (15/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
TABLE 2-1: PIC16F946 SPECIAL REGISTERS SUMMARY BANK 0
Addr Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR/BOR
Reset
Value on
all other
Resets⁽¹⁾
Bank 0
00h INDF
Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx xxxx xxxx
01h TMR0
Timer0 Module Register
xxxx xxxx uuuu uuuu
02h PCL
Program Counter’s (PC) Least Significant Byte
0000 0000 0000 0000
03h STATUS
IRP
RP1
RP0
TO
PD
Z
DC
C
0001 1xxx 000q quuu
04h FSR
Indirect Data Memory Address Pointer
xxxx xxxx uuuu uuuu
05h PORTA
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0 xxxx xxxx uuuu uuuu
06h PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0 xxxx xxxx uuuu uuuu
07h PORTC
RC7
RC6
RC5
RC4
RC3
RC2
RC1
RC0 xxxx xxxx uuuu uuuu
08h PORTD
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0 xxxx xxxx uuuu uuuu
09h PORTE
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0 xxxx xxxx uuuu uuuu
0Ah PCLATH
—
—
—
Write Buffer for upper 5 bits of Program Counter
---0 0000 ---0 0000
0Bh INTCON
GIE
PEIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF 0000 000x 0000 000x
0Ch PIR1
EEIF
ADIF
RCIF
TXIF
SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2
OSFIF
C2IF
C1IF
LCDIF
—
LVDIF
—
CCP2IF 0000 -0-0 0000 -0-0
0Eh TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1
xxxx xxxx uuuu uuuu
0Fh TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1
xxxx xxxx uuuu uuuu
10h T1CON
T1GINV T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 uuuu uuuu
11h TMR2
Timer2 Module Register
0000 0000 0000 0000
12h T2CON
— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register 1 (LSB)
xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register 1 (MSB)
xxxx xxxx uuuu uuuu
17h CCP1CON —
—
CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA
SPEN
RX9
SREN
CREN
ADDEN FERR
OERR
RX9D 0000 000x 0000 000x
19h TXREG USART Transmit Data Register
0000 0000 0000 0000
1Ah
1Bh⁽²⁾
1Ch⁽²⁾
1Dh⁽²⁾
RCREG USART Receive Data Register
CCPR2L Capture/Compare/PWM Register 2 (LSB)
CCPR2H Capture/Compare/PWM Register 2 (MSB)
CCP2CON —
—
CCP2X CCP2Y
CCP2M3
CCP2M2
CCP2M1
CCP2M0
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
1Eh ADRESH A/D Result Register High Byte
xxxx xxxx uuuu uuuu
1Fh ADCON0 ADFM VCFG1 VCFG0
CHS2
CHS1
CHS0 GO/DONE ADON 0000 0000 0000 0000
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 13