PIC16F946 Datasheet, PDF (83/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

FIGURE 4-7:
TWO-SPEED START-UP
Q1 Q2 Q3 Q4 Q1
INTOSC
TOST
OSC1
0
1 1022 1023
OSC2
Program Counter
PC
System Clock
Q2
Q3
PC + 1
PIC16F946
Q4
Q1
PC + 2
4.7 Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) is designed to
allow the device to continue to operate in the event of
an oscillator failure. The FSCM can detect oscillator
failure at any point after the device has exited a Reset
or Sleep condition and the Oscillator Start-up Timer
(OST) has expired.
FIGURE 4-8:
FSCM BLOCK DIAGRAM
Primary
Clock
LFINTOSC
Oscillator
÷ 64
Clock
Fail
Detector
Clock
Failure
Detected
The FSCM function is enabled by setting the FCMEN
bit in the Configuration Word (CONFIG). It is applicable
to all external clock options (LP, XT, HS, EC or RC
modes).
In the event of an external clock failure, the FSCM will
set the OSFIF bit (PIR2<7>) and generate an oscillator
fail interrupt if the OSFIE bit (PIE2<7>) is set. The
device will then switch the system clock to the internal
oscillator. The system clock will continue to come from
the internal oscillator unless the external clock recovers
and the Fail-Safe condition is exited.
The frequency of the internal oscillator will depend upon
the value contained in the IRCF bits (OSCCON<6:4>).
Upon entering the Fail-Safe condition, the OSTS bit
(OSCCON<3>) is automatically cleared to reflect that
the internal oscillator is active and the WDT is cleared.
The SCS bit (OSCCON<0>) is not updated. Enabling
FSCM does not affect the LTS bit.
The FSCM sample clock is generated by dividing the
INTOSC clock by 64. This will allow enough time
between FSCM sample clocks for a system clock edge
to occur. Figure 4-8 shows the FSCM block diagram.
On the rising edge of the sample clock, a monitoring
latch (CM = 0) will be cleared. On a falling edge of the
primary system clock, the monitoring latch will be set
(CM = 1). In the event that a falling edge of the sample
clock occurs, and the monitoring latch is not set, a clock
failure has been detected. The assigned internal
oscillator is enabled when FSCM is enabled as
reflected by the IRCF.
Note 1: Two-Speed Start-up is automatically
enabled when the Fail-Safe Clock Monitor
mode is enabled.
2: Primary clocks with a frequency ≤ ~488
Hz will be considered failed by the FSCM.
A slow starting oscillator can cause an
FSCM interrupt.
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 81