PIC16F946 Datasheet, PDF (169/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
REGISTER 14-2:
SSPCON – SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL SSPOV SSPEN
CKP
SSPM3 SSPM2 SSPM1 SSPM0
bit 7
bit 0
bit 7
bit 6
bit 5
bit 4
bit 3-0
WCOL: Write Collision Detect bit
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared
in software)
0 = No collision
SSPOV: Receive Overflow Indicator bit
In SPI™ mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of
overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read
the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the over-
flow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register.
0 = No overflow
In I²C™ mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t
care” in Transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
SSPEN: Synchronous Serial Port Enable bit
In SPI mode:
1 = Enables serial port and configures SCK, SDO and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I²C mode:
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In both modes, when enabled, these pins must be properly configured as input or output.
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level (Microwire default)
0 = Idle state for clock is a low level (Microwire alternate)
In I²C mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = FOSC/4
0001 = SPI Master mode, clock = FOSC/16
0010 = SPI Master mode, clock = FOSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I²C Slave mode, 7-bit address
0111 = I²C Slave mode, 10-bit address
1011 = I²C Firmware Controlled Master mode (slave idle)
1110 = I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
1111 = I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 167