PIC16F946 Datasheet, PDF (204/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
16.4 Interrupts
The PIC16F946 has multiple sources of interrupt:
• External Interrupt RB0/INT/SEG0
• TMR0 Overflow Interrupt
• PORTB Change Interrupts
• 2 Comparator Interrupts
• A/D Interrupt
• Timer1 Overflow Interrupt
• EEPROM Data Write Interrupt
• Fail-Safe Clock Monitor Interrupt
• LCD Interrupt
• PLVD Interrupt
• USART Receive and Transmit Interrupts
• CCP1 and CCP2 Interrupts
• TMR2 Interrupt
The Interrupt Control (INTCON) register and Peripheral
Interrupt Request 1 (PIR1) register record individual
interrupt requests in flag bits. The INTCON register
also has individual and global interrupt enable bits.
A Global Interrupt Enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. Individual interrupts can be
disabled through their corresponding enable bits in the
INTCON register and PIE1 register. GIE is cleared on
Reset.
The Return from Interrupt instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables unmasked interrupts.
The following interrupt flags are contained in the
INTCON register:
• INT Pin Interrupt
• PORTB Change Interrupt
• TMR0 Overflow Interrupt
The peripheral interrupt flags are contained in the special
registers, PIR1 and PIR2. The corresponding interrupt
enable bit are contained in the special registers, PIE1
and PIE2.
The following interrupt flags are contained in the PIR1
register:
• EEPROM Data Write Interrupt
• A/D Interrupt
• USART Receive and Transmit Interrupts
• Timer1 Overflow Interrupt
• CCP1 Interrupt
• SSP Interrupt
The following interrupt flags are contained in the PIR2
register:
• Fail-Safe Clock Monitor Interrupt
• Comparator 1 and 2 Interrupts
• LCD Interrupt
• PLVD Interrupt
• CCP2 Interrupt
When an interrupt is serviced:
• The GIE is cleared to disable any further interrupt.
• The return address is pushed onto the stack.
• The PC is loaded with 0004h.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends upon when the interrupt event occurs (see
Figure 16-8). The latency is the same for one or
two-cycle instructions. Once in the Interrupt Service
Routine, the source(s) of the interrupt can be
determined by polling the interrupt flag bits. The
interrupt flag bit(s) must be cleared in software before
re-enabling interrupts to avoid multiple interrupt
requests.
Note 1: Individual interrupt flag bits are set,
regardless of the status of their
corresponding mask bit or the GIE bit.
2: When an instruction that clears the GIE
bit is executed, any interrupts that were
pending for execution in the next cycle
are ignored. The interrupts, which were
ignored, are still pending to be serviced
when the GIE bit is set again.
For additional information on Timer1, A/D or data
EEPROM modules, refer to the respective peripheral
section.
Note:
The ANSEL (91h) and CMCON0 (9Ch)
registers must be initialized to configure
an analog channel as a digital input. Pins
configured as analog inputs will read ‘0’.
Also, if a LCD output function is active on
an external interrupt pin, that interrupt
function will be disabled.
DS41265A-page 202
Preliminary
© 2005 Microchip Technology Inc.