PIC16F946 Datasheet, PDF (206/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
FIGURE 16-8:
INT PIN INTERRUPT TIMING
OSC1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKO⁽³⁾
(4)
INT pin
INTF Flag
(1)
(INTCON<1>)
(1)
(5)
GIE bit
(INTCON<7>)
Interrupt Latency ⁽²⁾
Instruction Flow
PC
Instruction
Fetched
PC
Inst (PC)
PC + 1
Inst (PC + 1)
PC + 1
—
0004h
Inst (0004h)
0005h
Inst (0005h)
Instruction
Executed
Inst (PC - 1)
Inst (PC)
Dummy Cycle
Dummy Cycle
Inst (0004h)
Note 1:
2:
3:
4:
5:
INTF flag is sampled here (every Q1).
Asynchronous interrupt latency = 3-4 TCY. Synchronous latency = 3 TCY, where TCY = instruction cycle time.
Latency is the same whether Inst (PC) is a single cycle or a two-cycle instruction.
CLKO is available only in INTOSC and RC Oscillator modes.
For minimum width of INT pulse, refer to AC specifications in Section 19.0 “Electrical Specifications”.
INTF is enabled to be set any time during the Q4-Q1 cycles.
TABLE 16-6: SUMMARY OF INTERRUPT REGISTERS
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
Resets
0Bh, INTCON GIE PEIE T0IE INTE RBIE
8Bh
T0IF
INTF RBIF 0000 000x 0000 000x
0Ch PIR1 EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 OSFIF C2IF C1IF LCDIF — LVDIF
— CCP2IF 0000 -0-0 0000 -0-0
8Ch PIE1 EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 OSFIE C2IE C1IE LCDIE — LVDIE
— CCP2IE 0000 -0-0 0000 -0-0
Legend: x = unknown, u = unchanged, – = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the interrupt module.
DS41265A-page 204
Preliminary
© 2005 Microchip Technology Inc.