PIC16F946 Datasheet, PDF (179/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
14.12.2 RECEPTION
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
no Acknowledge (ACK) pulse is given. An overflow
condition is defined as either bit BF (SSPSTAT<0>) is
set, or bit SSPOV (SSPCON<6>) is set. This is an error
condition due to the user’s firmware.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in
software. The SSPSTAT register is used to determine
the status of the byte.
FIGURE 14-8:
I²C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
SDA
Receiving Address ^{R/W = 0}
Receiving Data
ACK
Receiving Data
ACK
A7 A6 A5 A4 A3 A2 A1
ACKD7 _{D6 D5 D4 D3 D2 D1 D0}
D7 D6 D5 D4 D3 D2 D1 D0
SCL S 1 2 ³ 4 5 ^{6 7} 8 ^{9 1 2 3 4 5 6 7 8 9 1 2 3} 4 ^{5 6 7 8 9}
P
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
Cleared in software
SSPBUF register is read
Bus Master
terminates
transfer
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 177