PIC16F946 Datasheet, PDF (13/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

2.0 MEMORY ORGANIZATION
2.1 Program Memory Organization
The PIC16F946 has a 13-bit program counter capable
of addressing an 8k x 14 program memory space
(0000h-1FFFh). The Reset vector is at 0000h and the
interrupt vector is at 0004h.
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16F946
pc<12:0>
CALL, RETURN
13
RETFIE, RETLW
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
0000h
On-chip
Program
Memory
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
0004h
0005h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
PIC16F946
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers (GPRs)
and the Special Function Registers (SFRs). Bits RP0
and RP1 are bank select bits.
RP0 RP1 (STATUS<6:5>)
= 00: → Bank 0
= 01: → Bank 1
= 10: → Bank 2
= 11: → Bank 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function
Registers are the General Purpose Registers,
implemented as static RAM. All implemented banks
contain Special Function Registers. Some frequently
used Special Function Registers from one bank are
mirrored in another bank for code reduction and
quicker access.
2.2.1
GENERAL PURPOSE REGISTER
FILE
The register file is organized as 336 x 8 in the
PIC16F946. Each register is accessed either directly or
indirectly through the File Select Register (FSR) (see
Section 2.5 “Indirect Addressing, INDF and FSR
Registers”).
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and peripheral functions for controlling the
desired operation of the device (see Tables 2-1,
2-2, 2-3 and 2-4). These registers are static RAM.
The special registers can be classified into two sets:
core and peripheral. The Special Function Registers
associated with the “core” are described in this section.
Those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 11