PIC16F946 Datasheet, PDF (111/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
9.3 LCD Multiplex Types
The LCD driver module can be configured into four
multiplex types:
• Static (only COM0 used)
• 1/2 multiplex (COM0 and COM1 are used)
• 1/3 multiplex (COM0, COM1 and COM2 are used)
• 1/4 multiplex (all COM0, COM1, COM2 and COM3
are used)
The LMUX<1:0> setting decides the function of RB5,
RA2 and RD0 pins (see Table 9-1 for details).
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. If the pin is a COM drive,
then the TRIS setting of that pin is overridden.
Note: On a Power-on Reset, the LMUX<1:0>
bits are ‘11’.
TABLE 9-1: RD0, RA2, RB5 FUNCTION
LMUX
<1:0>
RD0
RA2
RB5
00
Digital I/O Digital I/O Digital I/O
01
Digital I/O Digital I/O COM1 Driver
10
Digital I/O COM2 Driver COM1 Driver
11 COM3 Driver COM2 Driver COM1 Driver
9.4 Segment Enables
The LCDSEn registers are used to select the pin
function for each segment pin. The selection allows
each pin to operate as either an LCD segment driver or
as one of the pin’s alternate functions. To configure the
pin as a segment pin, the corresponding bits in the
LCDSEn registers must be set to ‘1’. See Figures 9-4
and 9-5 for more details.
If the pin is a digital I/O, the corresponding TRIS bit
controls the data direction. Any bit set in the LCDSEn
registers overrides any bit settings in the corresponding
TRIS register.
Note: On a Power-on Reset, these pins are
configured as digital I/O.
9.5 Pixel Control
The LCDDATAx registers contain bits which define the
state of each pixel. Each bit defines one unique pixel.
Register 9-4 shows the correlation of each bit in the
LCDDATAx registers to the respective common and
segment signals.
Any LCD pixel location not being used for display can
be used as general purpose RAM.
9.6 LCD Frame Frequency
The rate at which the COM and SEG outputs change is
called the LCD frame frequency.
TABLE 9-2: FRAME FREQUENCY
FORMULAS
Multiplex
Frame Frequency =
Static
1/2
1/3
1/4
Note:
Clock source/(4 x 1 x (LP<3:0> + 1))
Clock source/(2 x 2 x (LP<3:0> + 1))
Clock source/(1 x 3 x (LP<3:0> + 1))
Clock source/(1 x 4 x (LP<3:0> + 1))
Clock source is FOSC/8192, T1OSC/32 or
LFINTOSC/32.
TABLE 9-3:
LP<3:0>
2
3
4
5
6
7
APPROXIMATE FRAME
FREQUENCY (IN Hz) USING
FOSC @ 8 MHz, TIMER1 @
32.768 kHz OR INTOSC
Static
1/2
1/3
1/4
85
85
114
85
64
64
85
64
51
51
68
51
43
43
57
43
37
37
49
37
32
32
43
32
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 109