PIC16F946 Datasheet, PDF (143/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
FIGURE 11-4:
USART RECEIVE BLOCK DIAGRAM
FOSC
x64 Baud Rate CLK
SPBRG
Baud Rate Generator
RC7/RX/DT/
SDI/SDA/SEG8
Pin Buffer
and Control
CREN
÷64
or
÷16
OERR
FERR
MSb
RSR Register
Stop ₍₈₎ 7 _{• • •} 1 0
LSb
Start
Data
Recovery
RX9
SPEN
Interrupt
RX9D RCREG Register
FIFO
RCIF
RCIE
8
Data Bus
FIGURE 11-5:
RX (pin)
Rcv Shift
Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
ASYNCHRONOUS RECEPTION
Start
bit bit 0 bit 1
Start
bit 7/8 Stop bit bit 0
bit
Word 1
RCREG
Start
bit 7/8 Stop bit
bit
Word 2
RCREG
bit 7/8 Stop
bit
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word,
causing the OERR (Overrun Error) bit to be set.
TABLE 11-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR, BOR
Value on
all other
Resets
0Bh, 8Bh, INTCON GIE
10Bh,18Bh
PEIE T0IE INTE RBIE
T0IF
INTF
RBIF 0000 000x 0000 000x
0Ch
PIR1
EEIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
18h
RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x
1Ah
RCREG USART Receive Data Register
0000 0000 0000 0000
8Ch
PIE1
EEIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
98h
TXSTA CSRC TX9 TXEN SYNC
—
BRGH TRMT TX9D 0000 -010 0000 -010
99h
SPBRG Baud Rate Generator Register
0000 0000 0000 0000
Legend: x = unknown, – = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 141