PIC16F946 Datasheet, PDF (197/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
16.3.3 BROWN-OUT RESET (BOR)
The BOREN0 and BOREN1 bits in the Configuration
Word register selects one of four BOR modes. Two
modes have been added to allow software or hardware
control of the BOR enable. When BOREN<1:0> = 01,
the SBOREN bit (PCON<4>) enables/disables the
BOR allowing it to be controlled in software. By select-
ing BOREN<1:0>, the BOR is automatically disabled in
Sleep to conserve power and enabled on wake-up. In
this mode, the SBOREN bit is disabled. See
Register 16-1 for the Configuration Word definition.
If VDD falls below VBOR for greater than parameter
(TBOR) (see Section 19.0 “Electrical Specifica-
tions”), the Brown-out situation will reset the device.
FIGURE 16-3:
BROWN-OUT SITUATIONS
This will occur regardless of VDD slew rate. A Reset is
not insured to occur if VDD falls below VBOR for less
than parameter (TBOR).
On any Reset (Power-on, Brown-out, Watchdog Timer,
etc.), the chip will remain in Reset until VDD rises above
VBOR (see Figure 16-3). The Power-up Timer will now
be invoked, if enabled and will keep the chip in Reset
an additional 64 ms.
Note: The Power-up Timer is enabled by the
PWRTE bit in the Configuration Word.
If VDD drops below VBOR while the Power-up Timer is
running, the chip will go back into a Brown-out Reset
and the Power-up Timer will be re-initialized. Once VDD
rises above VBOR, the Power-up Timer will execute a
64 ms Reset.
VDD
VBOR
Internal
Reset
64 ms⁽¹⁾
VDD
VBOR
Internal
Reset
< 64 ms
64 ms⁽¹⁾
VDD
Internal
Reset
64 ms⁽¹⁾
Note 1: 64 ms delay only if PWRTE bit is programmed to ‘0’.
VBOR
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 195