PIC16F946 Datasheet, PDF (110/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

PIC16F946
9.1 LCD Clock Source Selection
The LCD driver module has 3 possible clock sources:
• FOSC/8192
• T1OSC/32
• LFINTOSC/32
The first clock source is the system clock divided by
8192 (FOSC/8192). This divider ratio is chosen to
provide about 1 kHz output when the system clock is
8 MHz. The divider is not programmable. Instead, the
LCD prescaler bits, LCDPS<3:0>, are used to set the
LCD frame clock rate.
The second clock source is the T1OSC/32. This also
gives about 1 kHz when a 32.768 kHz crystal is used
with the Timer1 oscillator. To use the Timer1 oscillator
as a clock source, the T1OSCEN (T1CON<3>) bit
should be set.
The third clock source is the 31 kHz LFINTOSC/32, which
provides approximately 1 kHz output.
The second and third clock sources may be used to
continue running the LCD while the processor is in
Sleep.
Using the bits, CS<1:0> (LCDCON<3:2>), any of these
clock sources can be selected.
9.1.1 LCD PRESCALER
A 16-bit counter is available as a prescaler for the LCD
clock. The prescaler is not directly readable or writable;
its value is set by the LP<3:0> bits (LCDPS<3:0>), which
determine the prescaler assignment and prescale ratio.
The prescale values from 1:1 through 1:16.
9.2 LCD Bias Types
The LCD driver module can be configured into three
bias types:
• Static Bias (2 voltage levels: VSS and VDD)
• 1/2 Bias (3 voltage levels: VSS, 1/2 VDD and VDD)
• 1/3 Bias (4 voltage levels: VSS, 1/3 VDD, 2/3 VDD
and VDD)
This module uses an external resistor ladder to
generate the LCD bias voltages.
The external resistor ladder should be connected to the
Bias 1 pin, Bias 2 pin, Bias 3 pin and VSS. The Bias 3
pin should also be connected to VDD.
Figure 9-2 shows the proper way to connect the
resistor ladder to the Bias pins.
Note:
VLCD pins used to supply LCD bias
voltage are enabled on power-up (POR)
and must be disabled by the user by
clearing LCDCON<4>, the VLCDEN bit,
(see Register 9-1).
FIGURE 9-2:
LCD BIAS RESISTOR LADDER CONNECTION DIAGRAM
VLCD 3 _To
VLCD 2 _LCD
VLCD 1
VLCD 0⁽¹⁾
Driver
VLCD 0
VLCD 1
VLCD 2
VLCD 3
Static
Bias
VSS
—
—
VDD
1/2 Bias 1/3 Bias
VSS
1/2 VDD
1/2 VDD
VDD
VSS
1/3 VDD
2/3 VDD
VDD
VDD*
VDD*
LCD Bias 3 LCD Bias 2 LCD Bias 1
10 kΩ*
10 kΩ*
Connections for External R-ladder
Static Bias
1/2 Bias
VSS
VDD*
10 kΩ*
10 kΩ*
10 kΩ*
1/3 Bias
VSS
* These values are provided for design guidance only and should be optimized for the application by the
designer.
Note 1: Internal connection.
DS41265A-page 108
Preliminary
© 2005 Microchip Technology Inc.