PIC16F946 Datasheet, PDF (205/274 Pages) Microchip Technology – 64-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt Technology

16.4.1 RB0/INT/SEG0 INTERRUPT
External interrupt on RB0/INT/SEG0 pin is edge-trig-
gered; either rising if the INTEDG bit (OPTION<6>) is
set, or falling, if the INTEDG bit is clear. When a valid
edge appears on the RB0/INT/SEG0 pin, the INTF bit
(INTCON<1>) is set. This interrupt can be disabled by
clearing the INTE control bit (INTCON<4>). The INTF
bit must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The
RB0/INT/SEG0 interrupt can wake-up the processor
from Sleep if the INTE bit was set prior to going into
Sleep. The status of the GIE bit decides whether or not
the processor branches to the interrupt vector following
wake-up (0004h). See Section 16.7 “Power-Down
Mode (Sleep)” for details on Sleep and Figure 16-10
for timing of wake-up from Sleep through
RB0/INT/SEG0 interrupt.
PIC16F946
16.4.2 TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
the T0IF (INTCON<2>) bit. The interrupt can be
enabled/disabled by setting/clearing T0IE
(INTCON<5>) bit. See Section 5.0 “Timer0 Module”
for operation of the Timer0 module.
16.4.3 PORTB INTERRUPT
An input change on PORTB sets the RBIF
(INTCON<0>) bit. The interrupt can be
enabled/disabled by setting/clearing the RBIE
(INTCON<3>) bit. Plus, individual pins can be
configured through the IOCB register.
Note:
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF
interrupt flag may not get set.
FIGURE 16-7:
INTERRUPT LOGIC
IOC-RB4
IOCB4
IOC-RB5
IOCB5
IOC-RB6
IOCB6
IOC-RB7
IOCB7
TMR2IF
TMR2IE
TMR1IF
TMR1IE
C1IF
C1IE
C2IF
C2IE
ADIF
ADIE
OSFIF
OSFIE
EEIF
EEIE
CCP1IF
CCP1IE
CCP2IF
CCP2IE
RCIF
RCIE
TXIF
TXIE
SSPIF
SSPIE
LCDIF
LCDIE
LVDIF
LVDIE
TMR0IF
TMR0IE
INTF
INTE
RBIF
RBIE
PEIF
PEIE
GIE
Wake-up (If in Sleep mode)
Interrupt to CPU
© 2005 Microchip Technology Inc.
Preliminary
DS41265A-page 203