IC43R16160 Datasheet, PDF (9/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
Output Data (DQ) and Data Strobe (DQS) Timing Relative to the Clock (CK)
During Read Cycles
(CAS Latency = 2.5; Burst Length = 4)
T0
T1
T2
T3
T4
CK, CK
Command
READ
NOP
DQS
DQ
NOP
NOP
NOP
t_DQSCK(max)
t_DQSCK(min)
t_AC(min)
t_AC(max)
D₀
D₁
D₂
D₃
The minimum time during which the output data (DQ) is valid is critical for the receiving device (i.e., a mem-
ory controller device). This also applies to the data strobe during the read cycle since it is tightly coupled to
the output data. The minimum data output valid time (t_DV) and minimum data strobe valid time (t_DQSV) are de-
rived from the minimum clock high/low time minus a margin for variation in data access and hold time due to
DLL jitter and power supply noise.
Integrated Circuit Solution Inc.
9
DDR001-0B 11/10/2004