IC43R16160 Datasheet, PDF (20/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
Data Mask Function
The DDR SDRAM has a Data Mask function that is used in conjunction with the Write cycle, but not the
Read cycle. When the Data Mask is activated (DM high) during a Write operation, the Write is blocked (Mask
to Data Latency = 0).
When issued, the Data Mask must be referenced to both the rising and falling edges of Data Strobe.
Data Mask Timing
(CAS Latency = Any; Burst Length = 8)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK, CK
Command
DQS
DQ
Write
NOP
t_DMDQSS
NOP
NOP
NOP
NOP
NOP
t_DMDQSS
NOP
t_DMDQSH
D₀ D₁ D₂ D₃ D₄ D₅ D₆ D₇
t_DMDQSH
DM
Burst Interruption
Read Interrupted by a Read
A Burst Read can be interrupted before completion of the burst by issuing a new Read command to any
bank. When the previous burst is interrupted, the remaining addresses are overridden with a full burst length
starting with the new address. The data from the first Read command continues to appear on the outputs until
the CAS latency from the interrupting Read command is satisfied. At this point, the data from the interrupting
Read command appears on the bus. Read commands can be issued on each rising edge of the system clock.
It is illegal to interrupt a Read with autoprecharge command with a Read command.
Read Interrupted by a Read Command Timing
(CAS Latency = 2; Burst Length = 4)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
CK, CK
Command
Read_A Read_B
NOP
NOP
NOP
NOP
NOP
NOP
DQS
DQ
DA0 DA1 DB0 DB1 DB2 DB3
20
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004