IC43R16160 Datasheet, PDF (45/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
Figure 38 - INITIALIZE AND MODE REGISTER SETS
VDD
VDDQ
VTT
(system*)
VREF
/CK
CK
CKE
COMMAND
DM
t _VTD
((
))
((
))
LVCMOS LOW LEVEL ( (
))
((
))
((
))
((
))
((
))
tCK
tCH tCL
tIS tIH
tIS tIH
NOP
PRE
A0-A9, A11
A10
BA0, BA1
DQS
DQ
((
))
((
))
((
))
((
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((
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((
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((
High-Z
))
((
High-Z
))
T = 200µs
ALL BANKS
tIS tIH
Power-up:
VDD and
CLK stable
((
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((
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((
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((
((
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EMRS _{( (}
MRS
((
PRE
((
AR
((
AR
))
))
))
))
((
((
((
((
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))
((
((
((
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tIS tIH
((
((
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((
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CODE
((
CODE
((
((
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))
tIS tIH
((
( ( ALL BANKS ( (
))
))
))
((
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CODE
((
CODE
((
((
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))
((
))
tIS tIH
tIS tIH
((
((
((
((
BA0=H,
) ) _BA0=L,
))
))
))
BA1=L ( (
BA1=L ( (
((
((
))
))
))
))
((
((
((
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((
((
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tMRD
tMRD
tRP
Extended
Mode
Register
Set
200 cycles of CLK**
Load
Mode
Register,
Reset DLL
(with A8 = H)
tRFC
* = VTT is not applied directly to the device, however tVTD must be greater than or equal to zero to avoid device latch-up.
** = tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be applied.
The two Auto Refresh commands may be moved to follow the first MRS, but precede the second PRECHARGE ALL command.
((
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MRS
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ACT
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((
CODE
RA
))
((
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((
CODE
RA
))
((
))
BA0=L,
((
BA1=L
BA
))
((
))
((
))
tRFC
tMRD
Load
Mode
Register
(with A8 = L)
DON'T CARE
Integrated Circuit Solution Inc.
45
DDR001-0B 11/10/2004