IC43R16160 Datasheet, PDF (2/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
4M Words x 16 Bits x 4 Banks (256-MBIT)
DDR SYNCHRONOUS DYNAMIC RAM
Clock Cycle Time (tCK2)
Clock Cycle Time (tCK2.5)
Clock Cycle Time (tCK3)
System Frequency (fCK max)
5
DDR400
7.5ns
6ns
5ns
200MHz
6
DDR333
7.5ns
6ns
-
166MHz
7
DDR266
7.5ns
7ns
-
143MHz
Features
■ High speed data transfer rates with system frequency
up to 200 MHz
■ Data Mask for Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 2.5, 3
■ Programmable Wrap Sequence: Sequential
or Interleave
■ Programmable Burst Length:
2, 4, 8 for Sequential Type
2, 4, 8 for Interleave Type
■ Automatic and Controlled Precharge Command
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 8192 cycles/64 ms
■ Available in 66-pin 400 mil TSOP
■ SSTL-2 Compatible I/Os
■ Double Data Rate (DDR)
■ Bidirectional Data Strobe (DQS) for input and output
data, active on both edges
■ On-Chip DLL aligns DQ and DQs transitions with CK
transitions
■ Differential clock inputs CK and CK
The ICSI IC43R16160 is a four bank DDR DRAM
organized as 4 banks x 4Mbit x 16. The IC43R16160
achieves high speed data transfer rates by employing a
chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, circuits are synchronized with
the positive edge of an externally supplied clock. I/O
transactions are ocurring on both edges of DQS. Operating
the four memory banks in an interleaved fashion allows
random access operation to occur at a higher rate than is
possible with standard DRAMs. A sequential and gapless
data rate is possible depending on burst length, CAS
latency and speed grade of the device.
Device Usage Chart
Operation
Temperature
Range
0°C to 70°C
Package Outline
JESEC 66TSOP II
•
CK Cycle Time (ns)
-5
-6
-7
•
•
•
Power
Std.
L
•
•
Temperature
Mark
Blank
2
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004