IC43R16160 Datasheet, PDF (6/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
Mode Register Set (MRS)
The mode register stores the data for controlling the various operating modes of DDR SDRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL reset and various vendor specific options to
make DDR SDRAM useful for a variety of different applications. The default value of the mode register is not
defined, therefore the mode register must be written after EMRS setting for proper DDR SDRAM operation.
The mode register is written by asserting low on CS, RAS, CAS, WE and BA₀ (The DDR SDRAM should be
in all bank precharge with CKE already high prior to writing into the mode register). The state of address pins
A₀ ~ A₁₂ in the same cycle as CS, RAS, CAS, WE and BA0 low is written in the mode register. Two clock
cycles are required to meet t_MRD spec. The mode register contents can be changed using the same com-
mand and clock cycle requirements during operation as long as all banks are in the idle state. The mode reg-
ister is divided into various fields depending on functionality. The burst length uses A₀ ~ A₂, addressing mode
uses A₃, CAS latency (read latency from column address) uses A₄ ~ A₆. A₈ is used for DLL reset. A7 must
be set to low for normal MRS operation. Refer to the table for specific codes for various burst length,
addressing modes and CAS latencies.
1. MRS can be issued only at all banks precharge state.
2. Minimum tRP is required to issue MRS command.
BA1 BA 0
A 12
to
A3
A2 A1 A0 ^{Address Bus}
0 MRS
RFU : Must be set "0"
I/O DLL Extended Mode Register
0 MRS
RFU
DLL
CAS Latency BT Burst Length
Mode Register
A8 DLL Reset
0
No
1
Yes
CAS Latency
BA0
An ~ A0
A6 A5 A4
0
(Existing)MRS Cycle
00 0
1
Extended Funtions(EMRS)
00 1
01 0
01 1
10 0
* RFU(Reserved for future use) ^{1 0 1}
should stay "0" during MRS
11 0
cycle.
11 1
A3 Burst Type
0 Sequential
1 Interleave
Latency
Reserve
Reserve
2
3
Reserve
Reserve
2.5
Reserve
Burst Length
A2 A1 A0
000
001
010
011
100
101
110
111
A1 I/O Strength
A0
0
Full
0
1
Half
1
Latency
Sequential Interleave
Reserve
Reserve
2
2
4
4
8
8
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
Reserve
DLL Enable
Enable
Disable
Mode Register Set
0
1
2
3
4
5
6
7
8
CK, CK
Command
Precharge
All Banks
tCK
tRP ^*2
*1
Mode
Register Set
t_MRD
Any
Command
6
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004