IC43R16160 Datasheet, PDF (32/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
AC Operating Conditions & Timming Specification
AC Operating Conditions
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS and DM signals
Input Low (Logic 0) Voltage, DQ, DQS and DM signals.
Input Differential Voltage, CK and CK inputs
Input Crossing Point Voltage, CK and CK inputs
Symbol
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
Min
VREF + 0.31
0.7
0.5*VDDQ-0.2
Max
VREF - 0.31
VDDQ+0.6
0.5*VDDQ+0.2
Unit
V
V
V
V
Note
1
2
3
4
Note:
1.Vih(max) = 4.2V. The overshoot voltage duration is < 3ns at VDD.
2. Vil(min) = -1.5V. The undershoot voltage duration is < 3ns at VSS.
3. VID is the magnitude of the difference between the input level on CK and the input on CK.
4. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the same.
ELECTRICAL CHARACTERISTICS AND AC TIMING for PC400/PC333/PC266/PC200 -Abso-
lute Specifications
(Notes: 1-5, 14-17) (0°C < T _A < 70°C; V_DDQ = +2.5V ±0.2V, +2.5V ±0.2V for DDR400 device V_DDQ = +2.6V ±0.1V, +2.5V
±0.1V)
AC CHARACTERISTICS
-5
-6
-7
PARAMETER
SYMBOL
Access window of DQs from CK/CK
CK high-level width
CK low-level width
Clock cycle time
CL = 3
CL = 2.5
CL = 2.5
t_AC
T_CH
T_CL
t_CK(3)
t_CK(2.5)
t_CK(2)
DQ and DM input hold time relative
to DQS
t_DH
DQ and DM input setup time
relative to DQS
t_DS
DQ and DM input pulse width (for
each input)
t_DIPW
Access window of DQS from
CK/CK
t_DQSCK
MIN
-0.65
0.45
0.45
5
6
7.5
0.40
0.40
1.75
-0.6
MAX
0.65
0.55
0.55
10
10
10
0.6
MIN
-0.7
0.45
0.45
-
6
7.5
0.45
0.45
1.75
-0.6
MAX
0.7
0.55
0.55
12
12
12
0.6
MIN
-0.75
0.45
0.45
-
7
7.5
0.50
0.50
1.75
-0.75
MAX
0.75
0.55
0.55
12
12
12
UNITS NOTES
ns
t_CK
30
t_CK
30
ns
48
ns
48
ns
48
ns
26,31
ns
26,31
ns
31
0.75 ns
DQS input high pulse width
t_{DQSH 0.35}
0.35
0.35
t_CK
DQS input low pulse width
DQS-DQ skew, DQS to last DQ
valid, per group, per access
Write command to first DQS
latching transition
DQS falling edge to CK rising -
setup time
t_{DQSL 0.35}
0.35
0.35
t_CK
t_DQSQ
0.4
0.45
0.5
ns
25,26
t_{DQSS 0.72 1.25 0.75 1.25 0.75 1.25} t_CK
t_DSS
0.2
0.2
0.2
t_CK
32
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004