IC43R16160 Datasheet, PDF (14/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
Precharge Timing During Read Operation
For the earliest possible Precharge command without interrupting a Read burst, the Precharge command
may be issued on the rising clock edge which is CAS latency (CL) clock cycles before the end of the Read
burst. A new Bank Activate (BA) command may be issued to the same bank after the RAS precharge time
(t_RP). A Precharge command can not be issued until t_RAS(min) is satisfied.
Read with Precharge Timing as a Function of CAS Latency
T0
T1
CK, CK
Command
BA NOP
T2
T3
t_RAS(min)
NOP
Read
T4
NOP
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
T5
T6
T7
T8
T9
t_RP(min)
Pre_A
NOP
BA
NOP
NOP
DQS
DQ
DQS
DQ
D₀ D₁ D₂ D₃
CAS Latency=2
D₀ D₁ D₂ D₃
CAS Latency=2.5
14
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004