IC43R16160 Datasheet, PDF (21/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
Read Interrupted by a Write
To interrupt a Burst Read with a Write command, a Burst Stop command must be asserted to stop the burst
read operation and 3-state the DQ bus. Additionally, control of the DQS bus must be turned around to allow
the memory controller to drive the data strobe signal (DQS) into the DDR SDRAM for the write cycles. Once
the Burst Stop command has been issued, a Write command can not be issued until a minimum delay or
latency (L_BST) has been satisfied. This latency is measured from the Burst Stop command and is equivalent
to the CAS latency programmed into the mode register. In instances where CAS latency is measured in half
clock cycles, the minimum delay (L_BST) is rounded up to the next full clock cycle (i.e., if CL=2 then L_BST=2, if
CL=2.5 then L_BST=3). It is illegal to interrupt a Read with autoprecharge command with a Write command.
Read Interrupted by Burst Stop Command Followed by a Write Command Timing
T0
CK, CK
Command
DQS
DQ
T1
Read
T2
T3
T4
BST
NOP
Write
D₀ D₁
L_BST
(CAS Latency = 2; Burst Length = 4)
T5
T6
T7
T8
T9
NOP
NOP
NOP
NOP
D₀ D₁ D₂ D₃
Write Interrupted by a Write
A Burst Write can be interrupted before completion by a new Write command to any bank. When the pre-
vious burst is interrupted, the remaining addresses are overridden with a full burst length starting with the new
address. The data from the first Write command continues to be input into the device until the Write Latency
of the interrupting Write command is satisfied (WL=1) At this point, the data from the interrupting Write com-
mand is input into the device. Write commands can be issued on each rising edge of the system clock. It is
illegal to interrupt a Write with autoprecharge command with a Write command.
Write Interrupted by a Write Command Timing
T0
CK, CK
Command
DQS
DQ
DM
T1
Write_A
T2
T3
T4
T5
Write_B
NOP
NOP
NOP
DA0 DA1 DB0 DB1 DB2 DB3
DM0 DM1 DM0 DM1 DM2 DM3
Write Latency
(CAS Latency = Any; Burst Length = 4)
T6
T7
T8
T9
NOP
NOP
NOP
Integrated Circuit Solution Inc.
21
DDR001-0B 11/10/2004