IC43R16160 Datasheet, PDF(22/56 Page) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

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IC43R16160 Datasheet, PDF (22/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

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IC43R16160

Write Interrupted by a Read

A Burst Write can be interrupted by a Read command to any bank. If a burst write operation is interrupted

prior to the end of the burst operation, then the last two pieces of input data prior to the Read command must

be masked off with the data mask (DM) input pin to prevent invalid data from being written into the memory

array. Any data that is present on the DQ pins coincident with or following the Read command will be masked

off by the Read command and will not be written to the array. The memory controller must give up control of

both the DQ bus and the DQS bus at least one clock cycle before the read data appears on the outputs in

order to avoid contention. In order to avoid data contention within the device, a delay is required (tCDLR) from

the last valid data input before a Read command can be issued to the device. It is illegal to interrupt a Write

with autoprecharge command with a Read command.

Write Interrupted by a Read Command Timing

(CAS Latency = 2; Burst Length = 8)

T10 T11 T12

CK, CK

Command

DQS

Write

NOP

tWTR

NOP

Read

NOP

D0 D1 D2 D3 D4 D5

D0 D1 D2 D3 D4 D5 D6 D7

Data is masked

by DM input

Data is masked

by Read command

DQS input ignored

Auto Refresh

The Auto Refresh command is issued by having CS, RAS, and CAS held low with CKE and WE high at the

rising edge of the clock. All banks must be precharged and idle for a tRP(min) before the Auto Refresh com-

mand is applied. No control of the address pins is required once this cycle has started because of the internal

address counter. When the Auto Refresh cycle has completed, all banks will be in the idle state. A delay be-

tween the Auto Refresh command and the next Activate command or subsequent Auto Refresh command

must be greater than or equal to the tRFC(min). Commands may not be issued to the device once an Auto

Refresh cycle has begun. CS input must remain high during the refresh period or NOP commands must be

registered on each rising edge of the CK input until the refresh period is satisfied.

Auto Refresh Timing

T10

T11

tRP

tRFC

CK, CK

Command

Pre All

Auto Ref

NOP NOP NOP ANY

CKE High

Integrated Circuit Solution Inc.

DDR001-0B 11/10/2004

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