IC43R16160 Datasheet, PDF(18/56 Page) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

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IC43R16160 Datasheet, PDF (18/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

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IC43R16160

Write Interrupted by a Precharge

A Burst Write can be interrupted before completion of the burst by a Precharge command, with the only

restriction being that the interval that separates the commands be at least one clock cycle.

Write Interrupted by a Precharge Timing

(CAS Latency = 2; Burst Length = 8)

T10 T11 T12

CK, CK

Command

DQS

WriteA NOP

NOP

NOP PreA

tWR

NOP NOP

NOP

D0 D1 D2 D3 D4 D5 D6

Data is masked

by DM input

Data is masked

by Precharge Command

DQS input ignored

Write with Auto Precharge

If A10 is high when a Write command is issued, the Write with auto Precharge function is performed. Any

new command to the same bank should not be issued until the internal precharge is completed. The internal

precharge begins after keeping tWR (min.).

Write with Auto Precharge Timing

(CAS Latency = Any; Burst Length = 4)

CK, CK

Command

BA NOP

tRAS(min)

NOP

WAP

NOP

T10

DQS

D0 D1 D2 D3

tWR(min)

tRP(min)

Begin Autoprecharge

Integrated Circuit Solution Inc.

DDR001-0B 11/10/2004

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