IC43R16160 Datasheet, PDF (15/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
Burst Stop Command
The Burst Stop command is valid only during burst read cycles and is initiated by having RAS and CAS
high with CS and WE low at the rising edge of the clock. When the Burst Stop command is issued during a
burst Read cycle, both the output data (DQ) and data strobe (DQS) go to a high impedance state after a delay
(L_BST) equal to the CAS latency programmed into the device. If the Burst Stop command is issued during a
burst Write cycle, the command will be treated as a NOP command.
Read Terminated by Burst Stop Command Timing
T0
CK, CK
Command
CAS Latency = 2
DQS
DQ
CAS Latency = 2.5
DQS
DQ
T1
T2
Read
BST
L_BST
L_BST
L_BST
(CAS Latency = 2, 2.5, 3; Burst Length = 4)
T3
T4
T5
T6
NOP
NOP
NOP
NOP
D₀ D₁
D₀ D₁
Integrated Circuit Solution Inc.
15
DDR001-0B 11/10/2004