IC43R16160 Datasheet, PDF (19/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
Precharge Timing During Write Operation
Precharge timing for Write operations in DRAMs requires enough time to satisfy the write recovery require-
ment. This is the time required by a DRAM sense amp to fully store the voltage level. For DDR SDRAMs, a
timing parameter (t_WR) is used to indicate the required amount of time between the last valid write operation
and a Precharge command to the same bank.
The “write recovery” operation begins on the rising clock edge after the last DQS edge that is used to strobe
in the last valid write data. “Write recovery” is complete on the next 2nd rising clock edge that is used to strobe
in the Precharge command.
Write with Precharge Timing
(CAS Latency = Any; Burst Length = 4)
T0
T1
CK, CK
Command
BA NOP
DQS
DQ
DQS
DQ
T2
T3
T4
T5
T6
t_RAS(min)
NOP
Write
NOP
NOP
NOP
D₀ D₁ D₂ D₃
D₀ D₁ D₂ D₃
T7
NOP
t_WR
t_WR
T8
Pre_A
T9
T10
t_RP(min)
NOP
BA
Integrated Circuit Solution Inc.
19
DDR001-0B 11/10/2004