IC43R16160 Datasheet, PDF (37/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
parameter, but system performance (bus turnaround) will degrade accordingly.
20. This is not a device limit. The device will operate with a negative value, but system performance could be
degraded due to bus turnaround.
21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS
going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous
WRITE was in progress, DQS could be HIGH during this time, depending on ^tDQSS.
22. MIN (^tRC or ^tRFC) for IDD measurements is the smallest multiple of ^tCK that meets the minimum absolute value
for the respective parameter. ^tRAS (MAX) for IDD measurements is the largest multiple of ^tCK that
meets the maximum absolute value for ^tRAS.
NOTES: (continued)
23. The refresh period 64ms. This equates to an average refresh rate of 7.8µs.
24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any
given device.
25. The valid data window is derived by achieving other specifications - ^tHP (^tCK/2), ^tDQSQ, and ^tQH
(^tQH = ^tHP - ^tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data
valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio.
26. Referenced to x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15.
27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command
period (^tRFC [MIN]) else CKE is LOW (i.e., during standby).
28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device..
30. CK and CK input slew rate must be •1V/ns.
31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less
than 0.5V/ns, timing must be derated: 50ps must be added to ^tDS and ^tDH for each 100mv/ns reduction in slew rate.
If slew rate exceeds 4V/ns, functionality is uncertain.
Integrated Circuit Solution Inc.
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DDR001-0B 11/10/2004