IC43R16160 Datasheet, PDF(17/56 Page) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

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IC43R16160 Datasheet, PDF (17/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

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IC43R16160

CK, CK

Burst Write Timing

(CAS Latency = Any; Burst Length = 4)

Command

DQS(nom)

DQ(nom)

DQS(min)

WRITE

NOP

tWPRES

tWPREH

tDQSS

tQDQSH

NOP

tQDQSS

NOP

tWPST

tQDQSH

tWPREH(min)

tWPRES(min)

tDQSS(min)

DQ(min)

DQS(max)

tWPRES(max)

tWPREH(max)

DQ(max)

tDQSS(max)

Once the burst of write data is concluded and given that no subsequent burst write operations are initiated,

the data strobe signal (DQS) transitions from a logic low level back to Hi-Z. This is referred to as the data

strobe âwrite postambleâ. This transition happens nominally one-half clock period after the last data of the

burst cycle is latched into the device.

Integrated Circuit Solution Inc.

DDR001-0B 11/10/2004

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