IC43R16160 Datasheet, PDF (44/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
The above characteristics are specified under best, worst and normal process variation/conditions
Figure 36 - DATA INPUT (WRITE) TIMING
tDSL tDSH
DQS
tDS
DQ
DI
n
tDH
tDS
DM
tDH
DON'T CARE
DI n = Data In for column n
Burst Length = 4 in the case shown
3 subsequent elements of Data In are applied in the programmed
order following DI n
Figure 37 - DATA OUTPUT (READ) TIMING
DQS
tDQSQ
max
tDQSQ
max
t _DQSQ
nom
DQ
tDQSQ
min
tDQSQ
min
1. tDQSQ max occurs when DQS is the earliest among DQS and DQ signals to transition.
2. tDQSQ min occurs when DQS is the latest among DQS and DQ signals to transition.
3. tDQSQ nom, shown for reference, occurs when DQS transitions in the center among DQ signal transitions.
DQS, DQ
tDV
Burst Length = 4 in the case shown
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Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004