IC43R16160 Datasheet, PDF (27/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
TRUTH TABLE 3 – Current State Bank n - Command to Bank m
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE /CS /RAS /CAS /WE
H
X
X
X
Any
L
H
H
H
Idle
X
X
X
X
L
L
H
H
Row Activating,
L
H
L
H
Active, or Precharging _L
H
L
L
L
L
H
L
Read
(Auto-Precharge
Disabled)
L
L
H
H
L
H
L
H
L
L
H
L
Write
(Auto- Precharge
Disabled)
L
L
H
H
L
H
L
H
L
H
L
L
L
L
H
L
L
L
H
H
Read
L
H
L
H
(With Auto-Precharge) _L
H
L
L
L
L
H
L
L
L
H
H
Write
L
H
L
H
(With Auto-Precharge) _L
H
L
L
L
L
H
L
COMMAND/ACTION
DESELECT (NOP/continue previous operation)
NO OPERATION (NOP/continue previous operation)
Any Command Otherwise Allowed to Bank m
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start new READ burst)
WRITE (select column and start WRITE burst)
PRECHARGE
ACTIVE (select and activate row)
READ (select column and start READ burst)
WRITE (select column and start new WRITE burst)
PRECHARGE
NOTES
7
7
7
7, 8
7
3a, 7
3a, 7, 9
3a, 7
3a, 7
NOTE:
1. This table applies when CKE_n-1 was HIGH and CKE_n is HIGH (see Truth Table 2) and after ^tXSR has been met
(if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the
commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and ^tRP has been met.
Row Active: A row in the bank has been activated, and ^tRCD has been met. No data
bursts/accesses and no register accesses are in progress.
Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and
has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and
has not yet terminated or been terminated.
Integrated Circuit Solution Inc.
27
DDR001-0B 11/10/2004