IC43R16160 Datasheet, PDF (38/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
32. VDD must not vary more than 4% if CKE is not active while any bank is active.
NOTES: (continued)
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount.
34. ^tHP min is the lesser of ^tCL minimum and ^tCH minimum actually applied to the device CK and CK/ inputs,
collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until ^tRAS(MIN) can be satisfied prior
to the internal precharge com-mand being issued.
36. Applies to x16. First DQS (LDQS or UDQS) to transition to last DQ (DQ0-DQ15) to transition valid.
Initial JEDEC specifications suggested this to be same as ^tDQSQ.
37. Normal Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum process, temperature and voltage
will lie within the outer bounding lines of the V-I curve of Figure A.
b) The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but no
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie
within the outer bounding lines of the V-I curve of Figure B.
d)The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not
guaranteed, to lie within the inner bounding lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be
between .71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0 Volt, and at the same voltage
and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10%, for device
drain-to-source voltages from 0.1V to 1.0 Volt.
38
Integrated Circuit Solution Inc.
DDR001-0B 11/10/2004