IC43R16160 Datasheet, PDF (51/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
Figure 44 - BANK READ ACCESS
/CK
CK
tIS tIH
CKE
tIS tIH
tCK
tCH tCL
COMMAND
NOP
ACT
NOP
NOP
NOP
x4:A0-A9
x8:A0-A8
x16:A0-A7
tIS tIH
RA
x4:A11
x8:A9, A11
RA
x16:A8, A9, A11
A10
RA
BA0, BA1
tIS tIH
Bank x
tRCD
tRAS
READ
NOP
PRE
Col n
NOP
NOP
tIS tIH
DIS AP
Bank x
CL = 2
ALL BANKS
ONE BANK
*Bank x
tRC
tRP
DM
ACT
RA
RA
RA
Bank x
Case 1:
tAC/tDQSCK = min
DQS
DQ
tRPRE
t _DQSCK
min
tRPST
tLZ
tHZ
min
DO
min
n
tLZ
tAC
min
min
Case 2:
tAC/tDQSCK = max
DQS
DQ
tRPRE
t _DQSCK
max
tRPST
tLZ
tHZ
max
DO
max
n
tLZ
t _AC
max
max
DO n = Data Out from column n
Burst Length = 4 in the case shown
3 subsequent elements of Data Out are provided in the programmed order following DO n
DIS AP = Disable Autoprecharge
* = "Don't Care", if A10 is HIGH at this point
PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address
NOP commands are shown for ease of illustration; other commands may be valid at these times
Note that tRCD > tRCD MIN so that the same timing applies if Autoprecharge is enabled (in which case tRAS would be limiting)
DON'T CARE
Integrated Circuit Solution Inc.
51
DDR001-0B 11/10/2004