IC43R16160 Datasheet, PDF (33/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM

IC43R16160
AC CHARACTERISTICS
-5
-6
-7
PARAMETER
SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES
DQS falling edge from CK rising -
hold time
t_DSH
0.2
0.2
Half clock period
t_HP
t_CH
t_CL
t_CH
t_CL
0.2 0.75
t_CK
t_CH
t_CL
ns
34
Data-out high-impedance window
from CK/CK
t_HZ
-0.65 0.65 -0.7 0.7 -0.75 0.75
ns
18
Data-out low-impedance window
from CK/ CK
t_LZ
-0.65 0.65 -0.7 0.7 -0.75 0.75
ns
18
Address and control input hold
time (fast slew rate)
t_IHF
0.6
0.75
0.9
ns
14
Address and control input setup
time (fast slew rate)
t_ISF
0.6
0.75
0.9
ns
14
Address and control input hold
time (slow slew rate)
t_IHs
0.7
0.8
1
ns
14
Address and control input setup
time (slow slew rate)
t_ISs
0.7
0.8
1
ns
14
LOAD MODE REGISTER
command cycle time
t_MRD
2.00
2.00
2.00
t_CK
DQ-DQS hold, DQS to first DQ to
non-valid,per access
t_QH
t_HP
-^tQHS
t_HP
-^tQHS
t_HP
-^tQHS
ns
25,26
Data hold skew factor
t_QHS
0.5
0.6
0.75
ns
ACTIVE to PRECHARGE com-
mand
t_RAS
40 70,000 42 120,000 45 120,000 ns
35
ACTIVE to READ with Auto pre-
charge command
t_RAP
t_{RAS(MIN) - (burst length *} t_CK/2)
ns
43
ACTIVE to ACTIVE/AUTO RE-
FRESH command period
t_RC
60
60
65
ns
AUTO REFRESH command period ^t_RFC
70
72
75
ns
46
ACTIVE to READ or WRITE delay ^t_RCD
15
18
15
ns
PRECHARGE command period
t_RP
15
18
15
ns
DQS read preamble
t_RPRE
0.9 1.1 0.9
1.1
0.9
1.1
t_CK
DQS read postamble
t_RPST
0.4 0.6 0.4
0.6
0.4
0.6
t_CK
ACTIVE bank a to ACTIVE bank b
command
t_RRD
10
12
15
DQS write preamble
t_{WPRE 0.25}
0.25
0.25
DQS write preamble setup time
t_WPRES
0
0
0
ns
t_CK
ns
20,21
Integrated Circuit Solution Inc.
33
DDR001-0B 11/10/2004