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IC43R16160 Datasheet, PDF (11/56 Pages) Integrated Circuit Solution Inc – 4M x 16 Bit x 4 Banks (256-MBIT) DDR SDRAM
IC43R16160
Data Strobe Preamble and Postamble Timings for DDR Read Cycles
(CAS Latency = 2; Burst Length = 2)
T0
T1
T2
T3
T4
CK, CK
Command
DQS
DQ
READ
NOP
tRPRE(min)
NOP
NOP
tRPRE(max)
tRPST(min)
tDQSQ(min)
tRPST(max)
D0
D1
tDQSQ(max)
Consecutive Burst Read Operation and Effects on the Data Strobe Preamble and Postamble
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
Command
DQS
DQ
ReadA
NOP
ReadB
NOP
NOP
NOP
NOP
NOP
D0A D1A D2A D3A D0B D1B D2B D3B
Burst Read Operation (CAS Latency = 2; Burst Length = 4)
CK, CK
Command
DQS
DQ
ReadA
NOP
NOP
ReadB
NOP
NOP
NOP
NOP
D0A D1A D2A D3A
D0B D1B D2B D3B
NOP
NOP
Integrated Circuit Solution Inc.
11
DDR001-0B 11/10/2004