HD6475328-CP10 Datasheet, PDF (83/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

Access to External Devices: The access cycle consists of three states. The data bus is 8 bits
wide. Figure 3-10 (a) and (b) shows the external access cycle. Additional wait states (Tw) can be
inserted by the wait-state controller (WSC).
3.7.2 On-Chip Memory Access Cycle
ø
Internal address bus
Internal Read signal
Internal data bus
(Read access)
Internal Write signal
Internal data bus
(Write access)
Memory cycle
T1 state
T2 state
Address
Read data
Write data
Figure 3-6 On-Chip Memory Access Timing
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