HD6475328-CP10 Datasheet, PDF (253/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

Bit 7—Overflow Flag (OVF): This bit indicates that the watchdog timer count has overflowed.
Bit 7
OVF
0
1
Description
This bit is cleared to from 1 to 0 when the CPU reads (Initial value)
the OVF bit, then writes a 0 in this bit.
This bit is set to 1 when TCNT changes from H'FF to H'00.
Bit 6—Timer Mode Select (WT/IT): This bit selects whether to operate in the watchdog timer
mode or interval timer mode.
Bit 6
WT/IT
0
1
Description
Interval timer mode (IRQ0 request)
Watchdog timer mode (NMI request)
(Initial value)
Bit 5—Timer Enable (TME): This bit enables or disables the timer.
Bit 5
TME
0
1
Description
TCNT is initialized to H'00 and stopped.
(Initial value)
TCNT runs. An interrupt is requested when the count overflows.
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight clock
sources obtained by dividing the system clock (ø).
The overflow interval listed in the table below is the time from when the watchdog timer counter
begins counting from H'00 until an overflow occurs.
In the interval timer mode, IRQ0 interrupts are requested at this interval.
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