HD6475328-CP10 Datasheet, PDF (179/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

A: Before Execution of BSET Instruction
Input/output
Pin state
DDR
DR
Pull-up
P5₇
Input
Low
0
1
On
P5₆
Input
High
0
0
Off
P5₅
Output
Low
1
0
Off
P5₄
Output
Low
1
0
Off
P5₃
Output
Low
1
0
Off
P5₂
Output
Low
1
0
Off
P5₁
Output
Low
1
0
Off
P5₀
Output
Low
1
0
Off
B: Execution of BSET Instruction
BSET.B #0
@PORT5
;set bit 0 in data register
C: After Execution of BSET Instruction
Input/output
Pin state
DDR
DR
Pull-up
P5₇
Input
Low
0
0
Off
P5₆
Input
High
0
1
On
P5₅
Output
Low
1
0
Off
P5₄
Output
Low
1
0
Off
P5₃
Output
Low
1
0
Off
P5₂
Output
Low
1
0
Off
P5₁
Output
Low
1
0
Off
P5₀
Output
High
1
1
Off
Explanation: To execute the BSET instruction, the CPU begins by reading port 5. Since P57 and
P56 are input pins, the CPU reads the level of these pins directly, not the value in the data register.
It reads P57 as low (0) and P56 as high (1).
Since P55 to P50 are output pins, for these pins the CPU reads the value in the data register (0).
The CPU therefore reads the value of port 5 as H'40, although the actual value in P5DR is H'80.
Next the CPU sets bit 0 of the read data to 1, changing the value to H'41.
Finally, the CPU writes this value (H'41) back to P5DR to complete the BSET instruction.
As a result, bit P50 is set to 1, switching pin P50 to high output. In addition, bits P57 and P56 are
both modified, changing the on/off settings of the MOS pull-up transistors of pins P57 and P56.
Programming Solution: The switching of the pull-ups for P57 and P56 in the preceding example
can be avoided by using a byte in RAM as a work area for P5DR, performing bit manipulations on
the work area, then writing the result to P5DR.
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