HD6475328-CP10 Datasheet, PDF (257/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

H’FF
TCNT
count
H’00
Time t
WT/IT = 0
TME = 1
IRQ0
request
IRQ0
request
IRQ0
request
IRQ0
request
IRQ0
request
Figure 13-4 Operation in Interval Timer Mode
13.3.3 Operation in Software Standby Mode
The watchdog timer has a special function in the software standby mode. Specific watchdog timer
settings are required when the software standby mode is used.
1. Before Transition to the Software Standby Mode: The TME bit must be cleared to 0 to stop
the watchdog timer counter before a transition to the software standby mode. The chip cannot
enter the software standby mode while the TME bit is set to 1. Before entering the software
standby mode, software should also set the clock select bits (CKS2 to CKS0) to a value that
makes the timer overflow interval equal to or greater than the settling time of the clock
oscillator.
2. Recovery from the Software Standby Mode: Recovery from the software standby mode can
be triggered by an NMI request. In this case the recovery proceeds as follows:
When an NMI request signal is received, the clock oscillator starts running and the watchdog
timer starts counting at the rate selected by the clock select bits before the software standby
mode was entered. When the count overflows (H'FF → H'00), the ø clock is presumed to be
stable and usable, clock signals are supplied to all modules on the chip, and the NMI interrupt-
handling routine starts executing. This timer overflow does not set the OVF flag, and the TME
bit remains cleared to 0.
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