HD6475328-CP10 Datasheet, PDF (381/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

B.2 Register Descriptions
Register name
Acronym of the register
Address to which the
register is mapped
SYSCR1—System Control Register 1
H'FEFC
Bit
numbers _Bit
7
6
5
4
3
2
1
— IRQ1E IRQ0E NMIEG BRLE —
—
Initial bit
values ^{Initial value}
1
0
0
0
0
1
1
Read/Write
—
R/W R/W R/W R/W
—
—
Name of the on-chip
supporting module
Port 1
0
—
Names of the
bits.
1
Dashes (—)
—
indicate
reserved bits.
Type of access permitted
R Read only
W Write only
R/W Both read and write
Bus Release Enable
0 P12 and P13 are I/O ports.
1 P12 is the BACK output pin. P13 is the BREQ input pin.
Full name of the bit
Nonmaskable Interrupt Edge
0 An NMI request is generated on the falling edge of the NMI pin input.
1 An NMI request is generated on the rising edge of the NMI pin input.
Functions of the bit settings
Interrupt Request 0 Enable
0 P15 is an I/O port; IRQ0 input is disabled.
1 P15 is the IRQ0 input pin.
Interrupt Request 1 Enable
0 P16 is an I/O port; IRQ1 input is disabled.
1 P16 is the IRQ1 input pin.
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