HD6475328-CP10 Datasheet, PDF (408/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

TCSR—Timer Status/Control Register
Bit
Initial value
Read/Write
7
OVF
0
R/(W)^*3
6
WT/IT
0
R/W
5
TME
0
R/W
H'FFEC^*1, H'FFED^*2
WDT
4
3
2
1
0
—
—
CKS2 CKS1 CKS0
1
1
0
0
0
—
—
R/W R/W R/W
Clock Select
0 0 0 ø/2
(51.2µs)^*4
0 0 1 ø/32 (819.2µs)
0 1 0 ø/64 (1.6ms)
0 1 1 ø/128 (3.3ms)
1 0 0 ø/256 (6.6ms)
1 0 1 ø/512 (13.1ms)
1 1 0 ø/2048 (52.4ms)
1 1 1 ø/4096 (104.9ms)
Timer Enable
0 Timer is disabled.
• TCNT is initialized to H'00 and stopped.
1 Timer is enabled.
• TCNT starts incrementing.
• CPU interrupt request is enabled.
Timer Mode Select
0 Interval timer mode (IRQ0 interrupt request)
1 Watchdog timer mode (NMI interrupt request)
Overflow Flag
0 Cleared from 1 to 0 when CPU reads OVF = 1, then wtites 0
in OVF.
1 Set to 1 when TCNT changes from H'FF to H'00.
*1 Read address
*2 Write address
*3 Only writing of 0 to clear the flag is enabled.
*4 Times in parentheses are the times for TCNT to increment from H'00 to H'FF and change to
H'00 again when ø = 10MHz.
399