HD6475328-CP10 Datasheet, PDF (202/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

Bit 2
OEA
0
1
Description
Output compare A output is disabled.
Output compare A output is enabled.
(Initial value)
Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for the FRC. External clock pulses are counted on the rising edge.
Bit 1 Bit 0
CKS1 CKS0 Description
0
0
Internal clock source (ø/4)
(Initial value)
0
1
Internal clock source (ø/8)
1
0
Internal clock source (ø/32)
1
1
External clock source (counted on the rising edge)*
* Output enable bit (bit 3) must be cleared to “0.”
10.2.5 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
ICF
0
R/(W)*
6
OCFB
0
R/(W)*
5
OCFA
0
R/(W)*
4
OVF
0
R/(W)*
3
OLVLB
0
R/W
2
OLVLA
0
R/W
1
IEDG
0
R/W
0
CCLRA
0
R/W
The TCSR is an 8-bit readable and partially writable* register that selects the input capture edge
and output compare levels, and specifies whether to clear the counter on compare-match A. It also
contains four status flags.
The TCSR is initialized to H'00 at a reset and in the standby modes.
* Software can write a “0” in bits 7 to 4 to clear the flags, but cannot write a “1” in these bits.
Bit 7—Input Capture Flag (ICF): This status flag is set to “1” to indicate an input capture
event. It signifies that the FRC value has been copied to the ICR.
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