HD6475328-CP10 Datasheet, PDF (209/459 Pages) Hitachi Semiconductor – original Hitachi CMOS microcomputer unit (MCU)

ø
Ø
FRC
N
OCR
N
N+1
Internal compare-
match signal
OCF
Figure 10-4 Setting of Output Compare Flags
Output Timing: When a compare-match occurs, the logic level selected by the output level bit
(OLVLA or OLVLB) in the TCSR is output at the output compare pin (FTOA or FTOB).
Figure 10-5 shows the timing of this operation for compare-match A.
ø
Internal compare-
match A signal
OLYLA
FTOA
Figure 10-5 Timing of Output Compare A
192